Electrostatic Discharge (ESD) is a potent killer of integrated circuits (IC's), and especially of IC's using Metal Oxide Semiconductors (MOS). There are various known strategies for protecting MOS IC's from ESD, among which is the one shown in FIG. 1. In FIG. 1 the bonded-out pads of an IC chip are denoted by large black squares, next to which appear associated generalized signal names for the corresponding pins on the IC package, such as SIG.sub.1, SIG.sub.2, GND and V.sub.DD. The figure shows output driver transistors that are connected between an output pad and ground (GND); for the sake of brevity, no loads or pull-up transistors are shown connected between these output pads and the power supply V.sub.DD, although it will be understood that such elements are present. Also, no input pads and associated circuitry are shown, as it will be likewise understood that these structures are also present on most IC's. Inputs are generally inherently more easily protectable than outputs, since it is usually possible to isolate the associated transistor from the input pad by some resistance. Nevertheless, let it be appreciated that inputs also are further protectable by the teachings set out below. It may be the case that typically the incremental benefit of further protecting an input is somewhat less than for further protecting an output, with its necessarily exposed driver transistor. So, we illustrate with outputs, with the understanding that our teachings are applicable to inputs, as well.
According to the strategy of FIG. 1, every pad of the IC chip except GND and V.sub.DD is provided with an ESD current path through, and with overvoltage protection with respect to, a common location. (That common location is GND, which is why it is one of the exceptions). The idea is that for an ESD event between any two pins on the IC package (GND and V.sub.DD excluded), the (electron or hole) current caused by an ESD event will travel from one of the pins toward GND, and away from GND toward the other pin.
FIG. 1 is associated with an IC that has a core (substrate) 1 of p material, and MOS Field Effect Transistors (FET's) whose sources and drains are of n material. This arrangement produces normally back biased parasitic diodes 2 and 3. There is a parasitic diode 2 associated with each output FET, such as FET 4 for SIG.sub.2 and FET 5 for SIG.sub.1 ; these are represented by diodes 6 and 7, respectively. Notice also the protective SCR's 8 and 9, which are in parallel with output FET's 4 and 5, respectively. The particular diode 3 shown in FIG. 1 normally never carries any current (it is shunted by the substrate 1 and its connection to GND), and is henceforth ignored. However, consider a FET whose drain is connected to V.sub.DD (say, to serve as a pull-up device for another FET whose source is at GND). It would have a parasitic diode from its source to the substrate 1 (just as diode 3, but without having a cathode permanently connected to GND), and that diode can be of interest. The collection of those particular parasitic diodes that are from V.sub.DD to the substrate I are represented by diode 10.
Before proceeding, it is well for us to set out specifically what is meant by the term GND (ground). The term GND is used herein to denote the electrically common point within the IC to which power supply return currents are routed and thence combined into one current that is returned to the power supply. There is usually a quite extensive collection of metal traces on the IC that connect various circuit elements to GND. We shall consider these traces to be GND as well, provided, of course, that there is no appreciable or significant voltage drop across them. Of course, GND is not the actual return side of the power supply itself. The IC is probably mounted on a printed circuit board, and the return currents for all of the appropriate circuits on the board are brought together. The return current for that board is then combined in a wiring harness or on a mother board with the return currents from other circuit boards; that point of combination may be called System GND (SGND). The actual point of return to the power supply is probably some significant physical distance away, and it and SGND may not be electrically equivalent to GND for any particular IC, owing to DC voltage drops and noise developed across the AC impedance of the return path. In the same spirit, we shall consider the substrate 1 an element or component that is connected to GND (and probably in lots of places, too), but that nevertheless is not itself GND. The reason is that while it may be a doped semiconductor whose extensive cross section makes it a relatively good conductor as semiconductors go, it is not a particularly good conductor in an absolute sense, say as is copper or aluminum.
Now consider an ESD event, such as the particular one depicted in FIG. 1. For this event the IC could be considered as lying unprotected on a table top, although that is not absolutely necessary. In the particular ESD event shown a source of negative charge 11 arcs to or is otherwise brought into contact with (zaps) the IC pin bonded to pad 12 for SIG.sub.1. A resulting (electron) current I.sub.IN travels inward toward GND and starts by going through the parasitic diode 7 associated with the transistor 5 that drives, or is connected to, the "start-from" pad 12. The anode of parasitic diode 7 is connected to GND. Once at GND I.sub.IN becomes I.sub.OUT and the remainder of the path to the "going-to" pad 13 (and thence to destination 15) is through a protection SCR 14 associated therewith, and that is provided for just this purpose. The SCR 14 must be triggered by a voltage sensing circuit (not shown), of which there is one for each such protective SCR (e.g., 8, 9).
The "spoke-hub-spoke" model described above can be examined for contact with positive charge on any single pin, as well as for negative charge on any single pin. In each case the path of the ESD current (of either holes or electrons, as appropriate) through a spoke will be either through a forward biased parasitic diode or through a triggered overvoltage protection SCR. There are, of course, a large number of possibilities with regard to how the ESD current can divide among the spokes. The current could go in toward the hub on a single spoke and out from the hub on several spokes. Likewise, it could go in on several spokes and out on just one, or it could go in on several and out on several. Also, the case of simple charge sharing must be remembered. This happens where a well insulated IC is zapped, and there occurs only an I.sub.IN or only an I.sub.OUT. Finally, it will be appreciated that in the case where the bulk substrate is of n material, all of the parasitic diodes and the protection SCR's are simply reversed, and a comparable spoke-hub-spoke structure obtains.
Before leaving FIG. 1 the reason can be mentioned why V.sub.DD is generally not included in the protection scheme outlined thus far. On the one hand, parasitic diodes 10 will take care of static zaps of one polarity, while breakdown of those diodes is relied upon for zaps of the other polarity. Relying upon such breakdown is not foolproof, but in comparison, there is a difficulty in incorporating a triggered switch such as an SCR into overvoltage protection for V.sub.DD : once an SCR is triggered on the gate loses control and the SCR cannot be simply "turned off". The result could be very bad news indeed for an IC zapped on V.sub.DD while the power was on.
A new consideration arises when it becomes desirable to provide separate power supply return paths for various circuits within the IC, as is shown in FIG. 2. The need to do this might arise out of noise immunity considerations, for example. Circuits that involve especially fast edges or particularly large currents are provided with separate return paths ("grounds") to the power supply. Such a separate ground is frequently referred to as a "dirty ground", since it may show significant system induced noise voltages when measured with respect to another location that is closer to or that actually is the return side of the power supply. We shall adopt the usual custom of denoting dirty ground as DGND. Although FIG. 2 depicts an IC having a single DGND, an IC might have more than one dirty ground. Let these be subscripted, thus: DGND.sub.1, DGND.sub.2, . . . . A remaining return path could be simply ground (GND), or it might make more sense to dispense with the label "GND" and treat any remaining return path as yet another instance of a DGND.sub.i. Still another scheme would be to refer to various GND.sub.i, some or all of which might be "dirty" and some not.
The labeling scheme chosen doesn't matter too much as long as it is not misleading. That is because when all is said and done, the various DGND's are simply separate return paths for selected circuits that terminate at their own pins, different from the pin for GND, and don't differ from GND in any significant internal detail, save one. That difference is that the meandering conductor that interconnects each of the circuit elements to be connected to GND is deposited directly onto the substrate, while conductors for dirty grounds are insulated from the substrate by an intervening glass layer (e.g., SiO.sub.2). From the pins of the IC the various grounds are routed by low-valued ohmic connections to a common location on the return side of the power supply. Naturally, the impedance of the DGND-GND connection is of interest in such an arrangement, so nothing is done that would make that impedance any larger than necessary. It is well to remember, however, that the most probable ESD situation of concern is not when the IC is installed on a PC board that is plugged into a mother board (connecting DGND to GND), but rather is when the IC is a solitary unprotected part, say on a table top. That situation is depicted in FIG. 3; but before turning to that, it will be useful to identify some additional features of interest in FIG. 2.
In FIG. 2 IC output signal pads 24 and 25 are driven by transistors 17 and 20, respectively. The power supply return for driver transistors 17 and 20 is provided by a pad 16 that is DGND. Note that it is known to include a protective SCR 23 with anode connected to DGND and cathode connected to GND. Diodes 18 and 21 are each an instance of parasitic diode 26. Resistances 19 and 22 represent resistances from the anodes of those parasitic diodes, through the bulk of the substrate, to the GND pad 27. In general, resistances 19 and 22 are not equal, and as distributed entities, may partially overlap so that a voltage developed across one is in part communicated to the other. Note also that DGND is not a hub in the sense that GND is; rather, DGND is at a distal end of a spoke whose other end is GND.
The conventional strategy of protective SCR's in spokes whose hub is GND, as described above, doesn't work as well as it ought to when used in IC's having one or more separate dirty grounds (DGND's). Because of resistance in the substrate, and apparently for other reasons that are not always clear, for those MOS IC's having p material substrates there is a definite additional risk of ESD damage to output driver structures that have an associated dirty ground and that are on the positive side of an ESD event. This leads to the hypothesis that the associated SCR is not getting turned on in time, or that if it is, it doesn't do any good. (Presumably, IC's with n material substrates and a dirty ground have a corresponding additional risk with negative zaps to output structures.)
Consider the situation shown in FIG. 3. As shown therein, a source of positive charge 29 zaps pad 24 whose driver transistor 17 operates with respect to DGND 16. The static zap of interest dissipates itself to DGND, as indicated schematically by the ground symbol 28. In this instance it is convenient to consider the currents I.sub.IN and I.sub.OUT as hole flow, rather than as an electron current. Thus, we show I.sub.IN proceeding from pad 24 to GND, and thence as I.sub.OUT from GND, through resistance 19 and parasitic diode 18 to DGND 16, and, on to the dissipative location 28. There will be a voltage drop across diode 18 and resistance 19, owing to the passage of I.sub.OUT. An additional source of voltage drop is to be found in the length of conductor 30 that ties the source of transistor 17 to the pad 16 for DGND. That length of conductor 30 has a resistance, in addition to a small residual inductance which can probably be ignored.
The significance of these various voltage drops mentioned in the preceding paragraph is that: (1) The voltage drop across the length of conductor 30 can elevate the source of transistor 17 above the potential of it surrounding elements, especially those coupled to the gate; and (2) Protective SCR 9, even when triggered, allows the voltage across transistor 17 to be as large as the sum of the voltage drops across diode 18, resistance 19 and the SCR 9 itself. Furthermore, note that if the trigger circuit of SCR 9 is referenced to GND 27, then the voltage drops across diode 18 and resistance 19 do not contribute to getting SCR 9 triggered. This manifests itself as a delay in getting SCR 9 triggered, which may increase the vulnerability of transistor 17. But even if SCR 9 is triggered without delay, with transient currents (I.sub.IN and I.sub.OUT) as high as several amperes, and with damage levels for voltage being fifteen or twenty volts, it doesn't take a very large impedance to produce damaging transient voltage drops across elements 18, 19 and 30 (and especially 19).
The situation is similar, although perhaps not quite as severe, if the source of charge 29 were negative instead of positive. In that case an electron current I.sub.IN would pass through diode 7 instead of SCR 9, and I.sub.OUT would be an electron current traveling from GND to DGND through protective SCR 23. The impedance of the length of conductor 30 would be of no interest. It would appear that protection of transistor 17 would depend principally upon getting SCR 23 triggered in time.
A solution to this problem is to equip each output structure (and input structures, too, if desired) with an additional protective SCR triggered with respect to the particular dirty ground servicing or associated that structure. It would also be advantageous if the additional SCR could be physically co-located with the conventional SCR referenced to GND. It will further be appreciated that the additional protective device need not necessarily be an SCR; other protective devices such as field oxide punch through devices, field emission devices, spark gaps, zeners and switched FET's could serve as the protective device. The important thing is that it would be connected between the pad whose transistors are to be protected and the associated dirty ground. Some further advantage may be gained by providing a protective device from other pads to DGND, even though the associated transistors for those pads are not served by DGND.
The techniques described herein can be especially useful in qualifying an integrated circuit under MIL-SPEC 883. That standard requires that each pin of an integrated circuit be electrically stressed with respect to every other pin, using the Human Body Model (a source of charge comprising 100 pfd in series with 1.5 Kohm) charged to either two kilovolts, four kilovolts, or greater than four kilovolts, according to a class of compliance desired. Since DGND is one of those pins in a chip that uses a dirty ground, protecting all the other pins just with respect to GND alone does not necessarily provide adequate protection for electrical stress of those pins with respect to DGND.
The preferred protective device is an SCR, which, of course, is something that must be triggered. That implies the use of trigger circuit, whose job it is to respond to an overvoltage between selected locations by triggering an SCR connected across those locations. A trigger circuit has a threshold, and ordinarily the threshold is set somewhat higher than V.sub.DD so that transients during power supply turn-on or noise during operation do not trip the trigger circuit. A greater degree of ESD protection for an uninstalled integrated circuit could be obtained if the trigger threshold were set as low as feasible, but to permanently set the threshold there would almost guarantee that the application of power would fire the SCR, rendering the IC unusable. The solution is a trigger circuit that has a threshold that varies as a function of V.sub.DD, say, V.sub.DD plus some approximately constant offset. In this way the trigger circuit is immune to V.sub.DD, and can use V.sub.DD as a signal to determine what the threshold should be.
Using V.sub.DD as a signal to select the threshold is effective, but is most easily done when neither of the two selected locations whose voltage difference is applied to the trigger circuit is itself V.sub.DD. That happy state of affairs obtains when the IC's substrate is of p-type material, since the combinations of IC pins of interest becomes pin to GND and pin to DGND. But for n-type substrates the combinations use V.sub.DD in place of GND (or DV.sub.DD in place of DGND). Since V.sub.DD is now assumed to be in the path of the ESD event, V.sub.DD is no longer a reliable source from which to determine trigger circuit threshold. What to do?
The solution is to recognize that the integrated circuit is really only in need of the lowest threshold when it is altogether uninstalled. That is, when an IC is installed on a printed circuit board its degree of vulnerability goes way down, owing to the dissapative ability of the additional external circuit environment. This means that if the absence of V.sub.DD can be used to establish the lower threshold while the presence of V.sub.DD sets the higher threshold, then the instance of V.sub.DD that is used for this purpose does not have to be taken from the conductors distributing V.sub.DD within the IC itself. Instead, it can enter the IC from the external environment by using a pin dedicated to that purpose. That is, that dedicated pin is only V.sub.DD when the IC is installed; when the IC is not installed it is not connected to V.sub.DD (except for its own ESD protection by diodes, which, it turns out, is not contrary the overall purpose). Thus, by means of an externally supplied separate (isolated) V.sub.DD brought in on its own pin of the IC, the trigger circuit can have a V.sub.DD -determined threshold, even when the substrate in of n-type material and V.sub.DD is one end of a potential to be compared to that threshold.